Publicaciones en las que colabora con JUAN CARLOS PICHEL CAMPOS (17)

2016

  1. Boosting performance of a Statistical Machine Translation system using dynamic parallelism

    Journal of Computational Science, Vol. 13, pp. 37-48

  2. Power and Energy Implications of the Number of Threads Used on the Intel Xeon Phi

    Annals of Multicore and GPU Programming: AMGP, Vol. 3, Núm. 1, pp. 55-65

2015

  1. Power and energy implications of the number of threads used on the Intel Xeon Phi

    Annals of Multicore and GPU Programming: AMGP, Vol. 2, Núm. 1, pp. 55-65

2014

  1. 3DyRM: a dynamic roofline model including memory latency information

    Journal of Supercomputing, Vol. 70, Núm. 2, pp. 696-708

  2. A hardware counter-based toolkit for the analysis of memory accesses in SMPs

    Concurrency Computation Practice and Experience, Vol. 26, Núm. 6, pp. 1328-1341

  3. Multiobjective optimization technique based on monitoring information to increase the performance of thread migration on multicores

    2014 IEEE International Conference on Cluster Computing, CLUSTER 2014

  4. Using an extended Roofline Model to understand data and thread affinities on NUMA systems

    Annals of Multicore and GPU Programming: AMGP, Vol. 1, Núm. 1, pp. 56-67

2013

  1. A flexible and dynamic page migration infrastructure based on hardware counters

    Journal of Supercomputing, Vol. 65, Núm. 2, pp. 930-948

2012

  1. A graphical tool for performance analysis of multicore systems based on the Roofline Model

    Proceedings of the 2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012

  2. Hardware counters based analysis of memory accesses in SMPs

    Proceedings of the 2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012

2011

  1. Analyzing the execution of sparse matrix-vector product on the Finisterrae SMP-NUMA system

    Journal of Supercomputing, Vol. 58, Núm. 2, pp. 195-205

2010

  1. Increasing the locality of iterative methods and its application to the simulation of semiconductor devices

    International Journal of High Performance Computing Applications, Vol. 24, Núm. 2, pp. 136-153

2009

  1. Increasing data reuse of sparse algebra codes on simultaneous multithreading architectures

    Concurrency Computation Practice and Experience, Vol. 21, Núm. 15, pp. 1838-1856

2005

  1. A new technique to reduce false sharing in parallel irregular codes based on distance functions

    Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN

  2. Performance optimization of irregular codes based on the combination of reordering and blocking techniques

    Parallel Computing, Vol. 31, Núm. 8-9, pp. 858-876

2004

  1. Improving the locality of the sparse matrix-vector product on shared memory multiprocessors

    Proceedings - Euromicro Conference on Parellel, Distribeted and Network-based Proceeding

  2. Mejora de la localidad en SMPs: el producto matriz dispersa-vector como caso de estudio

    Computación de altas prestaciones: actas de las XV Jornadas de Paralelismo. Almería 15, 16 y 17 de septiembre de 2004