Power and Energy Implications of the Number of Threads Used on the Intel Xeon Phi

  1. Lorenzo, O. G.
  2. Pena, T. F.
  3. Cabaleiro, J. C.
  4. Pichel, J. C.
  5. Rivera, F. F.
  6. Nikolopoulos, D. S.
Revista:
Annals of Multicore and GPU Programming: AMGP

ISSN: 2341-3158

Ano de publicación: 2016

Volume: 3

Número: 1

Páxinas: 55-65

Tipo: Artigo

Outras publicacións en: Annals of Multicore and GPU Programming: AMGP

Resumo

Energy consumption has become an important area of research of late. With the advent of new manycore processors, situations have arisen where not all the processors need to be active to reach an optimal relation between performance and energy usage. In this paper, a study of the power and energy usage of a series of benchmarks, the PARSEC and the SPLASH-2X Benchmark Suites, on the Intel Xeon Phi for different threads configurations, is presented. To carry out this study, a tool was designed to monitor and record the power usage in real time during execution time and afterwards to compare the results of executions with different number of parallel threads.

Referencias bibliográficas

  • Shao, Y.S., Brooks, D.: Energy characterization and instruction-level energy model of Intel's Xeon Phi processor. In: Proceedings
  • of the International Symposium on Low Power Electronics and Design, pp. 389{394 (2013). IEEE Press
  • Bienia, C.: Benchmarking modern multiprocessors. PhD thesis, Princeton University (January 2011)
  • Kogge, P., et al.: Exascale computing study: Technology challenges in achieving exascale systems. Technical report, DARPA
  • (2008)
  • Bedard, D., Lim, M.Y., Fowler, R., Portereld, A.: Powermon: Fine-grained and integrated power monitoring for commodity
  • computer systems. In: IEEE SoutheastCon 2010 (SoutheastCon), Proceedings of The, pp. 479{484 (2010). IEEE
  • Tolentino, M., Cameron, K.W.: The optimist, the pessimist, and the global race to exascale in 20 megawatts. Computer 45(1),
  • {97 (2012)
  • Kestor, G., Gioiosa, R., Kerbyson, D.J., Hoisie, A.: Enabling accurate power profiling of HPC applications on exascale systems. In:
  • ACM International Workshop on Runtime and Operating Systems for Supercomputers (2013)
  • Isci, C., Martonosi, M.: Runtime power monitoring in high-end processors: Methodology and empirical data. In: IEEE International
  • Symposium on Microarchitecture, MICRO{36 (2003)
  • Bertran, R., Gonzalez, M., Martorell, X., Navarro, N., Ayguade, E.: Decomposable and responsive power models for multicore
  • processors using performance counters. In: ACM International Conference on Supercomputing (2010)
  • Deshpande, A., Draper, J.: Leakage energy estimates for HPC applications. In: ACM International Workshop on Energy Efficient
  • Supercomputing. E2SC'13 (2013)
  • Li, B., Chang, H.-C., Song, S., Su, C.-Y., Meyer, T., Mooring, J., Cameron, K.W.: The power-performance tradeos of the Intel
  • Xeon Phi on HPC applications. In: Proc. 2014 IEEE Int. Parallel and Distributed Processing Symposium Workshops
  • (IPDPSW'14), pp. 1448{1456 (2014)
  • Leon, E.A., Karlin, I.: Characterizing the impact of program optimizations on power and energy for explicit hydrodynamics. In:
  • IEEE 28th International Parallel and Distributed Processing Symposium Workshops, pp. 773{781 (2014)
  • Nikolopoulos, D., Vandierendonck, H., Bellas, N., Antonopoulos, C., Lalis, S., Karakonstantis, G., Burg, A., Naumann, U.: Energy
  • efficiency through signifcance-based computing. Computer 47(7), 82{85 (2014)
  • Tiwari, A., Laurenzano, M.A., Carrington, L., Snavely, A.: Modeling power and energy usage of HPC kernels. In: IEEE 26th Int.
  • Parallel and Distributed Processing Symp. Workshops, pp. 990{998 (2012)
  • Seiler, L., Carmean, D., Sprangle, E., Forsyth, T., Abrash, M., Dubey, P., Junkins, S., Lake, A., Sugerman, J., Cavin, R., Espasa,
  • R., Grochowski, E., Juan, T., Hanrahan, P.: Larrabee: A many-core x86 architecture for visual computing. ACM Trans. Graph.
  • (3), 18{11815 (2008)
  • Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Iyer, P., Singh, A., Jacob, T., Jain, S.,
  • Venkataraman, S., Hoskote, Y., Borkar, N.: An 80-tile 1.28 TFLOPS network-on-chip in 65 nm CMOS. In: IEEE International
  • Solid-State Circuits Conference. Digest of Technical Papers, pp. 98{99. IEEE, San Francisco, USA (2007)
  • Rattner, J.: Single-chip Cloud Computer: An Experimental Many-core Processor from Intel Labs.
  • http://download.intel.com/pressroom/pdf/rockcreek/SCC Announcement JustinRattner.pdf
  • Intel Xeon Phi Coprocessor Datasheet.
  • http://www.intel.com/content/www/us/en/processors/xeon/xeon-phi-coprocessor-datasheet.html
  • R Development Core Team: R: A Language and Environment for Statistical Computing. R Foundation for Statistical Computing,
  • Vienna, Austria (2008). R Foundation for Statistical Computing. ISBN 3-900051-07-0