Publicacións (62) Publicacións de ELISARDO ANTELO SUAREZ

2019

  1. New 3D Projection Transformation for Point Clouds

    Proceedings - Symposium on Computer Arithmetic

2017

  1. A number system approach for adder topologies

    Proceedings - 24th IEEE Symposium on Computer Arithmetic, ARITH 2017

  2. A sum error detection scheme for decimal arithmetic

    Proceedings - 24th IEEE Symposium on Computer Arithmetic, ARITH 2017

  3. Improved 64-bit radix-16 booth multiplier based on partial product array height reduction

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, Núm. 2, pp. 409-418

2016

  1. Asymmetric allocation in a shared flexible signature module for multicore processors

    Computer Journal, Vol. 59, Núm. 10, pp. 1453-1469

2014

  1. Fast radix-10 multiplication using redundant BCD codes

    IEEE Transactions on Computers, Vol. 63, Núm. 8, pp. 1902-1914

2012

  1. FlexSig: Implementing flexible hardware signatures

    Transactions on Architecture and Code Optimization, Vol. 8, Núm. 4

  2. Guest editors' introduction: Special section on computer arithmetic

    IEEE Transactions on Computers

  3. Redundant floating-point decimal CORDIC algorithm

    IEEE Transactions on Computers, Vol. 61, Núm. 11, pp. 1551-1562

2011

  1. Foreword: ARITH-20

    Proceedings - Symposium on Computer Arithmetic

  2. Reducing the computation time in (short bit-width) two's complement multipliers

    IEEE Transactions on Computers, Vol. 60, Núm. 2, pp. 148-156

2010

  1. Improved design of high-performance parallel decimal multipliers

    IEEE Transactions on Computers, Vol. 59, Núm. 5, pp. 679-693

  2. Multi-Operand Decimal Addition by Efficient Reuse of a Binary Carry-Save Adder Tree

    2010 CONFERENCE RECORD OF THE FORTY FOURTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS (ASILOMAR)

  3. Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree

    Conference Record - Asilomar Conference on Signals, Systems and Computers

2009

  1. A Comment on "Beyond fat-tree: Unidirectional load-balanced multistage interconnection network"

    IEEE Computer Architecture Letters, Vol. 8, Núm. 1, pp. 33-34

  2. A high-performance significant BCD adder with IEEE 754-2008 decimal rounding

    Proceedings - Symposium on Computer Arithmetic

  3. Computation of decimal transcendental functions using the cordic algorithm

    Proceedings - Symposium on Computer Arithmetic

2008

  1. A low-latency pipelined 2D and 3D CORDIC processors

    IEEE Transactions on Computers, Vol. 57, Núm. 3, pp. 404-417

  2. New insights on ling adders

    Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

2007

  1. A new family of high - Performance parallel decimal multipliers

    Proceedings - Symposium on Computer Arithmetic