Publicacións nas que colabora con DAVID LOPEZ VILARIÑO (24)

2016

  1. PRECISION: A Reconfigurable SIMD/MIMD Coprocessor for Computer Vision Systems-on-Chip

    IEEE Transactions on Computers, Vol. 65, Núm. 8, pp. 2548-2561

2012

  1. Feature detection and matching on an SIMD/MIMD hybrid embedded processor

    IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops

  2. SIMD/MIMD dynamically-reconfigurable architecture for high-performance embedded vision systems

    Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

2009

  1. A digital cellular-based system for retinal vessel-tree extraction

    ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program

  2. FPGA-accelerated retinal vessel-tree extraction

    FPL 09: 19th International Conference on Field Programmable Logic and Applications

2008

  1. SIMD array on FPGA for B/W image processing

    Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications

2007

  1. CNN implementation of spin filters for electronic Speckle Pattern Interferometry applications

    Proceedings - IEEE International Symposium on Circuits and Systems

2006

  1. A binary-based on-chip CNN solution for pixel-level snakes

    International Journal of Circuit Theory and Applications, Vol. 34, Núm. 4, pp. 383-407

  2. On the reduction of the number of coefficient circuits in a DTCNN cell

    Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications

2005

  1. A one-quadrant discrete-Time cellular neural network architecture for pixel-Level snakes: B/W processing

    Proceedings - IEEE International Symposium on Circuits and Systems

  2. A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes

    Proceedings - IEEE International Symposium on Circuits and Systems

  3. On the emulation of large-neighborhood templates with binary cnn-based architectures

    Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications

2004

  1. A mixed-signal CMOS DTCNN chip for pixel-level snakes

    Proceedings - IEEE International Symposium on Circuits and Systems

  2. Design of the processing core of a mixed-signal CMOS DTCNN chip for pixel-level snakes

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 51, Núm. 5, pp. 997-1013

2003

  1. Cellular neural networks and active contours: A tool for image segmentation

    Image and Vision Computing, Vol. 21, Núm. 2, pp. 189-204

  2. Video segmentation for traffic monitoring tasks based on pixel-level snakes

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2652, pp. 1074-1081

2002

  1. An analogic CNN-algorithm of pixel level snakes for tracking and surveillance tasks

    Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications

  2. Implementation oriented theory design issues on the DTCNN template generation

    Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 3, pp. 101-104

  3. Robustness oriented design tool for multilayer DTCNN applications

    International Journal of Circuit Theory and Applications, Vol. 30, Núm. 2-3, pp. 195-210

2000

  1. DTCNN circuit proposal for pixel-level snakes

    Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications