Publicacións nas que colabora con Emilio López Zapata (32)

2002

  1. A configurable architecture for the wavelet packet transform

    Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 32, Núm. 3, pp. 255-273

  2. Architecture for wavelet packet transform based on lifting steps

    Parallel Computing, Vol. 28, Núm. 7-8, pp. 1023-1037

2001

  1. A data parallel formulation of the barnes-hut method for N−body simulations

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. A data-parallel formulation for divide and conquer algorithms

    Computer Journal, Vol. 44, Núm. 4, pp. 303-320

  3. Parallelization of a recursive decoupling method for solving tridiagonal linear systems on distributed memory computer

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2000

  1. An architecture for wavelet-packet based speech enhancement for hearing AIDS

    ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

  2. Architecture for wavelet packet transform with best tree searching

    Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

1999

  1. Area-efficient architecture for Fast Fourier Transform

    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 46, Núm. 2, pp. 187-193

1998

  1. A memory system supporting the efficient SIMD computation of the two dimensional DWT

    ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

  2. Algorithm for cosine transform of Toeplitz matrices

    Electronics Letters, Vol. 34, Núm. 12, pp. 1182-1183

1997

  1. A probabilistic model for best-first search B&B algorithms

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. High-performance VLSI architecture for the viterbi algorithm

    IEEE Transactions on Communications, Vol. 45, Núm. 2, pp. 168-176

  3. Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures

    Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 17, Núm. 1, pp. 57-73

  4. Mapping tridiagonal system algorithms onto mesh connected computers

    International Journal of High Speed Computing, Vol. 9, Núm. 2, pp. 101-126

  5. Unified framework for the parallelization of divide and conquer based tridiagonal systems

    Parallel Computing, Vol. 23, Núm. 6, pp. 667-686

1996

  1. FFTs on mesh connected computers

    Parallel Computing, Vol. 22, Núm. 1, pp. 19-38

  2. High performance VLSI architecture for the trellis coded quantization

    IEEE International Conference on Image Processing

  3. High-speed Viterbi decoder: an efficient scheduling method to exploit the pipelining

    International Conference on Application-Specific Systems, Architectures and Processors, Proceedings

1995

  1. A parallel architecture for the self-sorting FFT algorithm

    Journal of Parallel and Distributed Computing, Vol. 31, Núm. 1, pp. 88-97

  2. Constant geometry split-radix algorithms

    Journal of VLSI Signal Processing, Vol. 10, Núm. 2, pp. 141-152