Publicacións en colaboración con investigadores/as de Polytechnic University of Turin (8)

2017

  1. Improved 64-bit radix-16 booth multiplier based on partial product array height reduction

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, Núm. 2, pp. 409-418

2011

  1. Reducing the computation time in (short bit-width) two's complement multipliers

    IEEE Transactions on Computers, Vol. 60, Núm. 2, pp. 148-156

2010

  1. Improved design of high-performance parallel decimal multipliers

    IEEE Transactions on Computers, Vol. 59, Núm. 5, pp. 679-693

2007

  1. A new family of high - Performance parallel decimal multipliers

    Proceedings - Symposium on Computer Arithmetic

  2. A radix-10 SRT divider based on alternative BCD codings

    2007 IEEE International Conference on Computer Design, ICCD 2007

2005

  1. Digit-recurrence dividers with reduced logical depth

    IEEE Transactions on Computers, Vol. 54, Núm. 7, pp. 837-851

  2. Low latency digit-recurrence reciprocal and square-root reciprocal algorithm and architecture

    Proceedings - Symposium on Computer Arithmetic

2002

  1. Fast radix-4 retimed division with selection by comparisons

    Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors