Figures of merit that characterize silicon gate-all-around nanowire FETs affected by line edge roughness variability

  1. Garcia-Loureiro, Antonio 1
  2. Seoane, Natalia 1
  3. Fernandez, Julian G. 1
  4. Comesaña, Enrique 1
  5. Pichel, Juan C. 1
  1. 1 Universidade de Santiago de Compostela
    info

    Universidade de Santiago de Compostela

    Santiago de Compostela, España

    ROR https://ror.org/030eybx10

Editor: Zenodo

Ano de publicación: 2023

Tipo: Dataset

CC BY 4.0

DOI: 10.5281/ZENODO.7674909 lock_openAcceso aberto editor

Resumo

Off-current, threshold voltage, sub-threshold slope and on-current values for two silicon gate-all-around nanowire FETs affected by line edge roughness (LER) variability, a 22 nm gate length device and a 10 nm gate length one. The LER profile that characterizes the roughness deformation is also included in the dataset. Different correlation length (CL) and root mean square (RMS) heights values are characterized.