Low power CMOS vision sensors for scale and rotation invariant feature detectors using cmos heterogeneous smart pixel architectures

Abstract

The goal of the thesis is the implementation of the low level processing of the SIFT (Scale Invariant Feature Transform) algorithm into CMOS-3D technologies. The resultant chip will provide high speed of processing and low power consumption. In the thesis an in depth analysis of the SIFT algorithm will be done in order to determine the programmability of the several parameters of the algorithm. Later, a model of the system will be implemented including the possible error derived from the manufacturing processes to analyze their effects in the performance of the SIFT algorithm. With the information obtained from the analysis of the previous stages, the lowest level processing of the SIFT algorithm will be implemented. The lowest level stages will be added to higher level stages as well as the stages of acquisition, making up a vision chip into a CMOS-3D technology that implements the SIFT algorithm.