New hardware support for transactional memory and parallel debugging in multicore processors

  1. Lois Orosa Nogueira
unter der Leitung von:
  1. Javier Díaz Bruguera Doktorvater/Doktormutter
  2. Elisardo Antelo Suárez Doktorvater

Universität der Verteidigung: Universidade de Santiago de Compostela

Jahr der Verteidigung: 2013

  1. Ramón Doallo Präsident/in
  2. Francisco Fernández Rivera Sekretär
  3. Oscar Plata González Vocal
  4. Dora Blanco Heras Vocal
  5. João Manuel dos Santos Lourenço Vocal
  1. Departamento de Electrónica e Computación

Art: Dissertation


In the multicore era, parallel programming is become a must for programmers. However, parallel programming is intrinsically not intuitive and prone to errors. To face these drawbacks, it have arisen new tools to make this task easier by providing new parallel programming models and new debugging tools. Usually, all this new tools are not trivial, some of then require speculation or other complex mechanisms, which forces, in many cases, to add hardware support to achieve a reasonable performance. Among the hardware resources for accelerating these kind of tools, one of the most generally used in research papers, and therefore, with a lot of potential to be included in future general purpose processors, are signatures. A signature is a fixed piece of hardware that can host an unbounded number of addresses (using hash functions and allowing aliasing) in their storage elements, and it can check if a particular address was stored previously in the signature. This thesis contributes to the area of parallel programming hardware support by introducing new hardware elements in multicore processors, with the aim to accelerate an optimize new tools, abstractions and applications related with parallel programming in multicore processors, such as transactional memory and data race detectors. Specifically, we set up a Hardware Transactional Memory (HTM) system where signatures are part of the hardware support and we develop a new hardware filter based in minor modifications of the hardware, that allows to considerably reduce the signature size either their false positive rate (we call this filter CFM-TM). Under certain circumstances, the performance of the system it is also significantly improved. We also build the first hardware asymmetric data race detector (which also tolerates these races), called Pacman. Asymmetric data races are a very common type of data race that may cause dangerous concurrent bugs, and that until this work, it was explored only as a software approach. The hardware support of our detector is based on a centralized module of hardware signatures. We demonstrate that Pacman introduces negligible slowdowns in the system, and that it is able to efficiently detect and tolerate asymmetric data races. Finally, we propose a novel hardware signature module (called FlexSig) that solves some of the problems that we found when building our previous tools for multicore architectures based on signatures. Specifically, we design a signature module that can host a big number of signatures when there is a high demand of signatures, and also it can achieve a very low false positive rate when the demand of signatures is modest. We explore several strategies to allocate signatures in FlexSig to adapt to the different characteristics of the tools and applications that uses them. Concluding, we optimized the use of signatures in a HTM system introducing our CFM-TM filter, we develop a new debugging tool with signatures as main hardware support, and we build a new hardware signature module that allows a great flexibility in the size and number of allocated signatures, which fits in real scenario represented by a general purpose multicore processor executing a wide range of signature-demanding applications and tools.